搜索资源列表
USB2RAM
- Module usb ram - bardzo uzyteczny do komunikacji z innymi urzadzeniami-Module usb ram- bardzo uzyteczny do komunikacji z innymi urzadzeniami
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
control
- Turbo码编码器时序控制模块，能够对于RAM，ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
ZBTSRAM
- 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
dpram2
- vhdl写的双口ram，真正实现双口通信-I write vhdl dual ram, true dual-port communication
lpm_ram
- 一个基于quartus的LPM_RAM例子，VHDL语言写的，通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
SouceCode_0f_DDR_SDRAM_Controller_by_VHDL
- VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.
TESTRAM
- FPGA，双口RAM测试程序，仿真双口RAM工作时序，对时序的理解！适合对双口RAM不太了解的初学者使用！QUARTUSII8.0软件平台仿真通过！-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much
fifo_design
- 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
TechXclusives-ReconfiguringBlockRAMs
- Xilinx FPGA block RAM reconfig via JTAG
spmem.tar
- Sinlge port RAM VHDL/Verilog design
ram
- 代码实现了一个由32位寄存器组成的寄存器组，并有多个控制输入和两个输出，方便使用。-The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.
testRAMWR
- 这是一个用VHDL编写的读写双口RAM的程序.-This is a work written in VHDL to read and write dual-port RAM program.
spartan6_fpga_blockram_user_guide
- Spartan6 FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
components
- quartus的几个IP核（PWM,RAM,I2C）-quartus several IP core (PWM, RAM, I2C)
bram_delay
- Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file